1. Field of the Invention
The invention relates to thyristor devices, more particularly to an apparatus for triggering a plurality of thyristor devices into a conducting state.
2. Description of the Related Art
Referring to FIG. 1, which is a schematic electrical circuit diagram of an apparatus used to trigger a plurality of thyristor devices and which is disclosed in U.S. patent application Ser. No. 07/591,287 by the applicant, and to FIG. 2, which is a timing diagram illustrating the signal waveforms detected at different nodes of the circuit shown in FIG. 1, a rectifier circuit means (10) generates a full-wave rectified sinusoidal DC pulse signal from an AC supply input. The voltage signal at node (a) is the rectified pulse signal after it has passed through a resistor network. The voltage signal at node (a) serves as input to a Schmitt trigger (20). The output signal at node (b) of the Schmitt trigger (20) has a duration (T1) and is a pulse signal of constant amplitude which exists only when the voltage signal input thereto exceeds a certain DC voltage. The output signal at node (b) serves as input to a one-shot multivibrator (30). The output signal at node (c) of the one-shot multivibrator (30) is a delayed pulse signal having a duration (T2) which is shorter than the duration (T1).
A pulse generator (40) includes a toggle flip-flop (41), a clock generator (42) and a digital counter (43). The signal at node (c) triggers the flip-flop (41) so as to enable the clock generator (42) to generate a pulse train output at node (d). The digital counter (43) monitors the number of pulses produced by the clock generator (42). When the output bits (431) of the digital counter are at a high logic state, an AND logic gate (44) resets the digital counter (43) and the flip-flop (41). Once reset, the flip-flop (41) disables the clock generator (42). The clock generator (42) resumes the generation of the pulse train output when the flip-flop (41) is once more triggered by the next pulse signal at node (c).
The pulse train output at node (d) serves as input to an address counter (50). The address counter (50) has twelve output lines (Q11 to Q0). A memory unit (60) has eight data lines (D7-D0) and twelve address lines (A11 to A0) connected to the output lines (Q11 to Q0) of the address counter (50).
A decoder (70) has two input lines, which are connected to the most significant address lines (A11, A10) of the memory unit (60), and four output lines (f1-f4). The pulse outputs at the output lines (f1-f4) are shown in FIG. 2. A digital switch (80) has four 8-bit output sets (81-84) and eight input data lines connected to the data lines (D7-D0) of the memory unit (6). Each 8-bit output set (81-84) is selected according to the pulse output at the output lines (f1-f4). Once a particular output set (81-84) is selected, the logic states at the data lines (D7-D0) of the memory unit (60) are reflected at the selected output set. Each bit output of the four output sets (81-84) is connected to the gate electrode of a respective thyristor device (91) and supplies the triggering signal required to fire the thyristor device (91) into conduction. Each thyristor device (91) controls the passage of current from a power supply input through an electrical load (92).
Note that sixty-four memory spaces of the memory unit (60) are accessed each time a pulse train output is present at node (d) (there are sixty-four pulses in each pulse train output). Each of the thyristor devices (91) connected to the output sets (81-84) of the digital switch (80) therefore has sixteen trigger opportunities during each duration (T1). This triggering arrangement is not advisable for resistive loads (such as light bulbs) but is most favorable for inductive loads (such as motors). This is because inductive loads can improve the fluctuating current condition arising from this particular arrangement.
Although there are sixteen trigger opportunities available for each thyristor device (91), only one trigger opportunity is required so as to trigger the thyristor device (91) into conduction and maintain the same in a conducting state for the remainder of the duration (T1). The apparatus shown in FIG. 1 therefore has a relatively large memory requirement and makes inefficient use of said memory requirement. Furthermore, the apparatus shown in FIG. 1 is inadvisable for use in triggering a small number of thyristor devices.